气候变化领域集成服务门户(CCPortal): Experimental study on real-time measurement of single-event effects of 14 nm FinFET and 28 nm planar CMOS SRAMs based on Qinghai-Tibet Plateau

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DOI	10.7498/aps.72.20230161
	Experimental study on real-time measurement of single-event effects of 14 nm FinFET and 28 nm planar CMOS SRAMs based on Qinghai-Tibet Plateau
	Zhang, Zhan-Gang; Yang, Shao-Hua; Lin, Qian; Lei, Zhi-Feng; Peng, Chao; He, Yu-Juan
发表日期	2023
ISSN	1000-3290
卷号	72 期号:14
英文摘要	Based on the Yangbajing International Cosmic Ray Observatory in Lhasa with an altitude of 4300 m, a long-term real-time experiment is carried out in order to measure the atmospheric radiation induced soft errors in 14 nm FinFET and 28 nm planar CMOS SRAM array. The underlying mechanisms are also revealed. Five boards are used in the test, four of which are equipped with 28-nm process devices, and one board is equipped with 14-nm process devices. After removing the unstable bad bits, the actual effective test capacity is 7.1 Gb. During the test, the on-board FPGA reads the stored contents of all the tested devices in real time, reports the error information (occurrence time, board number, column number, device number, error address, error data) and corrects the error. The duration of the test is 6651 h. A total of 56 single event upset (SEU) events are observed, they being 24 single bit upset (SBU) events and 32 Multiple Cell Upset (MCU) events. Based on previous results of 65-nm SRAM, the study finds that SER continues to decrease with the reduction of process size, but the proportion of MCU in 28-nm process devices (57%) exceeds SBU, which is a process maximum point of MCU sensitivity, and the maximum size of MCU is 16 bits. Although the Fin spacing of the 14-nm FinFET device is only about 35 nm, and the critical charge decreases to sub-fC, the introduction of the FinFET structure leads to the change of charge collection and the sensitive volume sharing mechanism , and the shallow trench isolation leads to the narrowing of the charge diffusion channel. On the other hand, the surface area of the sensitive volume decreases to 0.0024 & mu;m2, resulting in a significant decrease in the soft error rate of both SBU and MCU in the 14-nm process.
关键词	FinFET neutron single event upset soft error
英文关键词	MULTIPLE-CELL UPSETS; ALTITUDE; BIT
WOS研究方向	Physics, Multidisciplinary
WOS记录号	WOS:001045012400020
来源期刊	ACTA PHYSICA SINICA
文献类型	期刊论文
条目标识符	http://gcip.llas.ac.cn/handle/2XKMVOVA/283567
推荐引用方式 GB/T 7714	Zhang, Zhan-Gang,Yang, Shao-Hua,Lin, Qian,et al. Experimental study on real-time measurement of single-event effects of 14 nm FinFET and 28 nm planar CMOS SRAMs based on Qinghai-Tibet Plateau[J],2023,72(14).
APA	Zhang, Zhan-Gang,Yang, Shao-Hua,Lin, Qian,Lei, Zhi-Feng,Peng, Chao,&He, Yu-Juan.(2023).Experimental study on real-time measurement of single-event effects of 14 nm FinFET and 28 nm planar CMOS SRAMs based on Qinghai-Tibet Plateau.ACTA PHYSICA SINICA,72(14).
MLA	Zhang, Zhan-Gang,et al."Experimental study on real-time measurement of single-event effects of 14 nm FinFET and 28 nm planar CMOS SRAMs based on Qinghai-Tibet Plateau".ACTA PHYSICA SINICA 72.14(2023).